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TDA7317
FIVE BANDS DIGITAL CONTROLLED GRAPHIC EQUALIZER
ADVANCE DATA
VOLUME CONTROL IN 0.375dB STEP FIVE BANDS STEREO GRAPHIC EQUALIZER CENTER FREQUENCY, BANDWIDTH, MAX BOOST/CUT DEFINED BY EXTERNAL COMPONENTS 14dB CUT/BOOST CONTROL IN 2dB/STEP ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS VERY LOW DISTORTION VERY LOW NOISE AND DC STEPPING BY USE OF A MIXED BIPOLAR/CMOS TECHNOLOGY DESCRIPTION The TDA7317 is a monolithic, digitally controlled graphic equalizer realized in BiCMOS mixed technology. The stereo signal, before any filtering, can be atBLOCK DIAGRAM
SDIP30 ORDERING NUMBER: TDA7317
tenuated up to -17.625dB in 0.375dB step. All the functions can be programmed via serial bus making easy to build a P controlled system. Signal path is designed for very low noise and distortion.
November 1993
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TDA7317
PIN CONNECTION
ABSOLUTE MAXIMUM RATINGS
Symbol VS Top Tstg R tjvins Supply Voltage Operating Temperature Range Storage Temperature Range Thermal Resistance Junction pins max Parameter Value 10.2 -40 to +85 -55 to +150 85 Unit V C C C/W
ELECTRICAL CHARACTERISTICS (Tamb = 25C, VS = 9V, RL = 10K, Rg = 600, f = 1KHz VIN = 1Vrms, all controls in flat position (AV = 0dB) unless otherwise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection f = 300Hz to 10KHz 6 8 60 9 14 80 10 20 V mA dB
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TDA7317
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT
RI VIN max IN S Input Resistance Max Input Signal Input Separation (1) THD = 0.3% 20 2 80 30 2.5 100 40 K VRMS dB
VOLUME CONTROL
C RANGE AVMIN AVMAX ASTEP EA ET VDC Control Range Min. Attenuation Max. Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps adjacent attenuation steps 0 -0.5 16.7 0.175 -1 17.625 0 17.625 0.375 0.5 18.6 0.575 1 0.5 3 dB dB dB dB dB dB mV
GRAPHIC EQUALIZER
THD Cs e NO Distortion Channel Separation Output Noise BW = 20Hz to 20KHz flat, AV = 0dB A curve BW = 20Hz to 20KHz AV = 0dB All bands = max. boost All bands = max. cut S/N Bstep C RANGE VDC Signal to Noise Ratio Step Resolution Control Range DC Steps max boost/cut Adiacent Control Steps AV = 0dB; Vref = 1V RMS 1 12 80 0.01 100 8 6 24 6 100 2 14 0.5 3 16 3 20 0.1 % dB V V V V dB dB dB mV
AUDIO OUTPUTS
VO RL CL RO VOUT Output Voltage Output Load Resistance Output Load Capacitance Output Resistance DC Voltage Level 5 4.2 10 4.5 THD = 0.3% 2 2 10 20 4.8 2.5 VRMS K nF V
BUS INPUTS
VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 +5 0.4 1 V V A V
ADDRESS PIN (Internal 50K pull down resistor)
VIL VIH Input Low Voltage Input High Voltage VCC -1V 1 V V
NOTE: The input is grounded thru the 2.2P capacitors
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TDA7317
DEVICE DESCRIPTION The TDA7317 is a five bands, digitally controlled stereo Graphic Equalizer. The device is intended for high quality audio application in Hi-Fi, TV and car radio systems where feature like low noise and THD are key factors. A mixed Bipolar Cmos Technology allows: Cmos analog switches for pop free commutations, high frequency op.amp. (GWB = 10MHz) and high linearity polisilicon resistor for THD = 0.01 (at Vin = 1Vrms) and a S/N ratio of 102dB. The internal Block Diagram is shown on page 1. The first stage is a volume control. The control range is 0 to -17.625dB with 0.375dBstep. The very high resolution (0.375dB step) allows the implementation of closed loop amplitude control system completely free from any acustical effect (stepping variation and pumping effect). The volume control is followed by a serial five bands equalizer. Each filtering cell is the biquad cell shown in fig. 1 The internal resistor string is fixing the boost/cut value while the buffer makes the Q (quality factor) and central frequency, set by external components, fully indipendent from the internal resistors. Each filtering cell is realized using only 4 external components (2 capacitors and 2 resistors) allowing a flexible selection of centre frequency fo, Q factor and gain. Here below the basic formulae and the key features of each band pass filter are reported: fo = center frequency Gv = gain/loss at the center frequency fo Gv = 20log(Av) Fig. 1 Q= fo f2 - f1
where f2, f1 = 3dB Bandwidth limits. Av = (R2 C2 ) + (R2 C1 ) + (R1 C1 ) (R2 C1 ) + (R2 C2 ) Q= fo = (R1 C1 R2 C2 ) (R2 C1 ) + (R2 C2 )
1 2 (R1 R2 C1 C2)
If C1 is fixed, then: C2 = R2 = Q2 Av - 1 - Q2 1 2 C1 fo R1 = (Av -1 ) Q (Av - 1 - Q2) R2 C1
(Av - 1)2 Av - 1 - Q2
Likewise, the components'values can be determined by fixing one of the other three parameters. Referring to fig. 1 the suggested R2 value should be higher than 2K in order to have a good THD (internal op. amp. current limit). Viceversa the R1 value should be equal or lower than 51K in order to keep the "click"(DC step) very low. A typical application is shown by fig. 2
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TDA7317
Figure 2: Application Circuit
The five bands graphic equalizer is used in conjunction with a TDA7318 (or another audioprocessor of the SGS-THOMSON 731X family). The audioprocessor bass and treble tone can furnish two extra filter bands. Application requiring higher number of external equalizer bands could be implemented by cascading 2 or more TDA7317 devices. In fact the
dedicated ADDR pin allows 2 addresses selection. Anyway, the address of the graphic equalizer is different from the audioprocessor one. For example 11 bands are implemented by use of 2 TDA7317 plus an audioprocessor (TDA731X family). In case one filtering cell is not needed, a short circuit must be provided between the P1xy and P2xy pins.
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TDA7317
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7317 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
2 Figure 3: Data Validity on the I CBUS
Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it generates the 9th clock pulse without checking the slave acknowledging, and then sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Figure 4: Timing Diagram of I2CBUS
Figure 5: Acknowledge on the I2CBUS
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TDA7317
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7317 address (the 8th bit of the byte must be 0). The TDA7317 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
TDA7316 ADDRESS MSB S 1 0 first byte 0 0 0 1 A LSB 0 ACK MSB DATA LSB
AC K
MSB DATA
LSB
AC P K
Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION Chip address (84 or 86 Hex)
1 MSB 0 0 0 0 1 A 0 LSB
A = Logic level on pin ADDR
A = 1 if ADDR pin = open A = 0 if ADDR pin = connected to ground SOFTWARE SPECIFICATION (continued) DATA BYTES (detailed description) Volume
MSB 0 X B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 X B2 0 0 0 0 1 1 B1 0 0 1 1 0 0 B0 0 1 0 1 0 1 A2 A1 0 0 1 1 0 0 1 1 A1 LSB A0 0 1 0 1 0 1 0 1 A0 FUNCTION Volume 0.375dB steps 0 -0.375 -0.75 -1.125 -1.5 -1.875 -2.25 -2.625 Volume -3dB steps 0 -3 -6 -9 -12 -15
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TDA7317
Graphic Equalizer
MSB 1 D3 0 0 0 0 1 D3 D3 D2 0 0 1 1 0 D2 D2 D1 0 1 0 1 0 D1 D1 1 0 C2 C2 0 0 0 0 1 1 1 1 C1 C1 0 0 1 1 0 0 1 1 C0 C0 0 1 0 1 0 1 0 1 D0 S2 C1 LSB C0 Band Band Band Band Band cut Boost 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 1 2 3 4 5 FUNCTION
AX = 0.375dB steps, BX = 3dB steps, CX = 2dB steps, X = dont'care
STATUS AFTER POWER-ON RESET Volume Graphic equalizer bands -17.25dB -12dB
APPLICATION INFORMATION A typical application is indicated in figure 4, while TABLE 1: Max Boost/cut = 20 dB (each cell = 14dB)
F (HZ) BAND 1 BAND 2 BAND 3 BAND 4 BAND 5 10363.38 261.03 1036.34 3168.08 59.75 Q 1.49 1.49 1.49 1.49 1.11 R1 (K) 47 47 47 47 43
the P.C. Board and components layout are reported in figure 5. The external components, are calculated for 2 different max boost/cut conditions
R2 (K) 5.1 5.1 5.1 5.1 7.5
C1 (nF) 0.820 33 8.2 2.7 220
C2 (nF) 1.2 47 12 3.9 100
Av max (dB) 13.52 13.63 13.52 13.57 13.88
For THD performance the sequence Band 1, 2, 3, 4, 5, is recommended
TABLE2: Max Boost/cut = 17dB (each cell = 12dB)
F (HZ) BAND 1 BAND 2 BAND 3 BAND 4 BAND 5 10158.00 250.81 977.34 3429.00 61.82 Q 1.15 1.21 1.20 1.25 1.15 R1 (K) 33 30 39 39 33 R2 (K) 6.2 5.1 6.8 6.2 6.2 C1 (nF) 1.2 47 10 2.7 180 C2 (nF) 1 56 10 3.3 180 Av max (dB) 11.83 11.33 11.75 11.67 11.27
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TDA7317
Figure 4
Figure 5: PCP Board and components layout of the figure 4 (scale 1:1)
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TDA7317
Measurements done on the test jig of fig. 5 using the components indicated in table2, are reported Figure 6: Frequency Response in figg. 6, 7,8. Figure 7 THD vs Frequency Max Boost/cut = :14dB
Figure 8: Cross Talk vs Frequency
Purchase of I2C Components of SGS-THOMSON Microlectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
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TDA7317
SDIP30 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B B1 C D E E1 e e1 L M S 0.31 2.54 0.51 3.05 0.36 0.76 0.20 27.43 10.16 8.38 3.81 0.46 0.99 0.25 27.94 10.41 8.64 1.778 10.16 3.30 3.81 0.10 4.57 0.56 1.40 0.36 28.45 11.05 9.40 mm TYP. MAX. 5.08 0.020 0.12 0.014 0.030 0.008 1.08 0.400 0.330 0.15 0.018 0.039 0.01 1.10 0.410 0.340 0.070 0.400 0.13 0.15 0.18 0.022 0.055 0.014 1.12 0.435 0.370 MIN. inch TYP. MAX. 0.20
0(min.), 15(max.) 0.012
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TDA7317
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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